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H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019 Remarks:

 All the coursework has to be done in VHDL. Coursework handed in using another language will be marked as zero.

 Coursework must be typeset.  Never use screenshots or photograph of code in your coursework. Typeset code within your

coursework report using a monospace font (e.g. courier new).  Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include

a high resolution screenshot in your coursework.

a) Consider the register bank of the educational processor (file cpuregbank.vhd of labcpu):

The objective is to create a testbench for this circuit, and simulate the a few operations including storing data in it as well as retrieving data from it.

In order to do this, use the file cpuregbank.vhd which is in labcpu zipfile. The file dffre.vhd is also required as it is used internally by the register bank.

H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019

The ports of cpuregbank are:

clk : in STD_LOGIC; — Clock rst : in STD_LOGIC; — Reset signal (active high) d : in STD_LOGIC_VECTOR(7 downto 0) — Data to write to a register

— (when rwren is enabled) rwren : in STD_LOGIC — Set to 1 to write d into register rwr rwr : in STD_LOGIC_VECTOR(1 downto 0) — Selects which register to write to. — The register encoding is identical — to that used in the assembler

— instruction encoding. rrd1 : out STD_LOGIC_VECTOR(1 downto 0) — Select which register is

— mapped to q1 rrd2 : out STD_LOGIC_VECTOR(1 downto 0) — Select which register is

— mapped to q2 q1 : out STD_LOGIC_VECTOR(7 downto 0) — Content of register selected by rrd1 q2 : out STD_LOGIC_VECTOR(7 downto 0) — Content of register selected by rrd2 dbg_qa : in STD_LOGIC_VECTOR(7 downto 0) — This is a debug signal which has

— the content of register RA. It is — used in the lab to display the — register content on the 7-segment — display. (A production processor — would not have this signal)

dbg_qb : in STD_LOGIC_VECTOR(7 downto 0) — Same as dbg_qa but for RB dbg_qc : in STD_LOGIC_VECTOR(7 downto 0) — Same as dbg_qa but for RC dbg_qd : in STD_LOGIC_VECTOR(7 downto 0) — Same as dbg_qa but for RD

First, your test-bench should ensure a regular clock is driving clk with a clock period of 100ns, and a 50% duty cycle.

Then, the testbench should allow to test a variety of operations the sequence described hereafter.

i) Reset: The test bench should first reset the register bank. The reset is synchronous. It should also set rrd1, rrd2, d, rwr, rwren to zero.

ii) Store1: store the value 0x55 to register RA

iii) Store2: store the value 0xAA to register RB

iii) Store3: store the value 0xFF to register RC

iv) Load1: get the content of register RA on q1 and RB on q2

v) Load2: get the content of register RC on q1 and RD on q2

In the coursework report:

i) Explain the testbench file you constructed, what it does, and how it does it. In order to do that, provide the complete source of the testbench, and in the main text of your report explain the testbench file. By “explaining the testbench”, we ask you to first provide an overall explanation of how you intend to simulate the system, and then explain the purpose of each of the VHDL constructs you are using to realise the tests indicated above. Make sure you explain where the Reset, Store1, Store2, Store3, Load1, Load2 operations take place.

Note: if you create the testbench from Vivado’s user interface, a lot of default comments are inserted by Vivado. Remove these, as they are not useful for this coursework.

H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019

ii) Provide a screen capture of the waveforms resulting from the testbench. All signals must be legible. Make sure that all the values in the waveforms are legible and in hex. Note: do not take photographs! Use a proper screen capture tool, such as pressing the “Print Screen” key. Explain what can be observed on these waveforms. Make sure you highlight on the waveform (e.g. with mspaint) where the operations Reset, Store1, Store2, Store3, Load1, Load2 operations take place.

All the register bank signals must be visible in the waveform.

[20 marks (10 marks for the testbench and associated explanation, 10 marks for the waveform and associated explanations; if the testbench does not work, not marks will be

assigned)]

b) Consider an input signal (i.e. a square wave) which has a maximum frequency of 1MHz. We want to count how many times the input signal transitioned from 0 to 1.

Detail three approaches to count the number of transitions.

i) the first approach should be a pure digital circuit (i.e. no processor).

ii) the second approach should consist only of a processor (UoS educational processor).

iii) the third approach should be a combination of processor (UoS educational processor) and a digital circuit (e.g. interfaced on the external I/O bus), both working together to acquire the number of transitions. You have significant flexibility here in finding an implementation that offers an advantage compared to (i) and (ii) in some interesting way. As a hint, consider that the input signal could have potentially a much higher clock frequency than the one at which the processor operates.

In the report:

i) explain the implementation of your system in a way that another engineer would understand it. In particular, provide schematic for variant (i) and (iii) and provide assembler code for variant (ii) and (iii). Explain your choice, and how your implementation works.

Make sure in the report that you do provide the code and schematic, and explain in the core text what the code or circuit does, and how.

ii) discuss the advantages and disadvantages of each approach.

[20 marks (5 marks per implementation with comments, 5 mark for the indentification of advantages and disadvantages]

c) The Sussex Educational Processor executes an instruction every 3 clock cycles. Explain why that is the case and specifically what happens during each of these three clock cycles.

[5 marks]

d) Explain and justify what is the maximum addressable memory for the processor using the mov instruction (note that this is not the amount of available memory, which was 32 bytes in the labs; it’s the maximum amount of memory which could be ‘touched’ by the processor).

[5 marks]

e) You are provided with the following VHDL code of a logic gate:

H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019

entity something is port ( clk : in STD_LOGIC; s : in STD_LOGIC; r : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC); end something; architecture Behavioral of something is begin process(clk) begin if s=’1′ then q<=’1′; else if clk’event and clk=’0′ then if r=’1′ then q <= ‘0’; else q <= not d; end if; end if; end if; end process; end Behavioral;

The resulting logic gate is a variation of a type of gate commonly used in digital systems. Explain what is this logic gate and how it behaves.

[5 marks]

f) Write an assembler program that performs a loop exactly n times, with the value n specified on 8-bits on the external interface. Write down: i) the assembler code; ii) an explanation of what the assembler code does, line by line.

[10 marks (5 marks for the program, 5 for the explanations)]

g) Consider the program below. Explain line by line the operation performed by the instruction and the resulting register values for registers RA, RB, RC, RD. Write the value that is in the register after the execution of the instruction in the corresponding column; if the value is unknown indicated this with ??. Assume we do not know the content of the registers on program start.

RA RB RC RD mov rb,32h . . . . xor rd,rd . . . . sub rd,rb . . . . shr rb . . . . asr rd . . . .

[5 marks (1 mark per correct line)]

h) You are provided with the following memory dump. Write the assembler instructions corresponding to this memory dump.

H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019

Address Data 00 1330 02 3303 04 5770 06 B10A 08 B002

[5 marks (1 per correct instruction)]

i) Explain how many total number of ALU operations could be realised in the UoS Educational Processor if you modified the cpualu.vhd keeping the current structure of the instruction encoding, and provide an explanation for your answer.

[5 marks]

j) Consider the instruction “MOV [RB], RD” (assume RA=08h,RB=55h,RC=37h,RD=A0h). Assume we are shortly before the clock edge of the “execute” cycle (i.e. at the next rising edge the instruction will be executed).

By analyzing the VHDL code of the processor, explain what happens inside the educational processor to execute this instruction. Specifically, indicate the state of the following signals (or indicate if undefined):

instruction (in cpu.vhd) rrd1 (port of cpuregbank in cpu.vhd) rrd2 (port of cpuregbank in cpu.vhd) rwr (port of cpuregbank in cpu.vhd) d (port of cpuregbank in cpu.vhd) reg1out (in cpu.vhd) reg2out (in cpu.vhd) source (in cpu.vhd) regwren (in cpu.vhd) flagwren (in cpu.vhd) ram_we (in cpu.vhd) ram_address (in cpu.vhd) ram_datawr (in cpu.vhd) op (port of cpualu in cpu.vhd) a (port of cpualu in cpu.vhd) b (port of cpualu in cpu.vhd) aluqout (in cpu.vhd) alufout (in cpu.vhd) wrdata (in cpu.vhd) finally, summarize the overall processor behavior with this instruction.

[20 marks (1 mark per correct signal value, 1 mark for a correct explanation)]

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